#ifndef QBL_ADAPTER_PANIC_H__
#define QBL_ADAPTER_PANIC_H__
/******************************************************************************
 Copyright (c) 2020 - 2023 Qualcomm Technologies International, Ltd.
 All Rights Reserved.
 Qualcomm Technologies International, Ltd. Confidential and Proprietary.

******************************************************************************/

#ifdef __cplusplus
extern "C" {
#endif

#if defined(HYDRA) || defined(CAA)

#if 0
#define PANIC_INVALID_BLUESTACK_PRIMITIVE          CSR_BT_PANIC_INVALID_BLUESTACK_PRIMITIVE
#endif

#else

#define panic(p) BLUESTACK_PANIC(p)

#define PANIC_MYSTERY                                       CSR_BT_PANIC_MYSTERY
#define PANIC_MBLK_MAP_ERROR                                CSR_BT_PANIC_MBLK_MAP_ERROR
#define PANIC_L2CAP_HCI_DATA_CREDITS_INCONSISTENT           CSR_BT_PANIC_L2CAP_HCI_DATA_CREDITS_INCONSISTENT
#define PANIC_INVALID_BLUESTACK_PRIMITIVE                   CSR_BT_PANIC_INVALID_BLUESTACK_PRIMITIVE
#define PANIC_INVALID_ESCO_TX_INTERVAL                      CSR_BT_PANIC_INVALID_ESCO_TX_INTERVAL
#define PANIC_HEAP_EXHAUSTION                               CSR_BT_PANIC_HEAP_EXHAUSTION
#define PANIC_MBLK_MSGFRAG_COALESCE_FAILURE                 CSR_BT_PANIC_MBLK_MSGFRAG_COALESCE_FAILURE
#define PANIC_MBLK_DISCARD_TAIL_ERROR                       CSR_BT_PANIC_MBLK_DISCARD_TAIL_ERROR
#define PANIC_RFCOMM_TIMER_ALREADY_STARTED                  CSR_BT_PANIC_RFCOMM_TIMER_ALREADY_STARTED
#define PANIC_RFCOMM_INVALID_TIMER_TYPE                     CSR_BT_PANIC_RFCOMM_INVALID_TIMER_TYPE
#define PANIC_RFCOMM_INVALID_TIMER_CONTEXT                  CSR_BT_PANIC_RFCOMM_INVALID_TIMER_CONTEXT
#define PANIC_MBLK_CREATE_FAILURE                           CSR_BT_PANIC_MBLK_CREATE_FAILURE
#define PANIC_RFCOMM_L2CAP_REGISTER_FAILED                  CSR_BT_PANIC_RFCOMM_L2CAP_REGISTER_FAILED
#define PANIC_RFCOMM_STREAM_MISMATCH                        CSR_BT_PANIC_RFCOMM_STREAM_MISMATCH
#define PANIC_DM_ACL_LOCKS_EXHAUSED                         CSR_BT_PANIC_DM_ACL_LOCKS_EXHAUSED
#define PANIC_INVALID_ULP_BUFFER_SIZE_RESPONSE              CSR_BT_PANIC_INVALID_ULP_BUFFER_SIZE_RESPONSE
#define PANIC_SM_L2CAP_HANDLER                              CSR_BT_PANIC_SM_L2CAP_HANDLER
#define PANIC_ATT_INVALID_STATE                             CSR_BT_PANIC_ATT_INVALID_STATE
#define PANIC_ATT_INVALID_TYPE                              CSR_BT_PANIC_ATT_INVALID_TYPE
#define PANIC_DM_INVALID_HANDLE                             CSR_BT_PANIC_DM_INVALID_HANDLE
#define PANIC_ATT_FIXED_CID_REG_FAILED                      CSR_BT_PANIC_ATT_FIXED_CID_REG_FAILED
#define PANIC_ATT_MARSHAL_UNMARSHAL_INVALID_STATE           CSR_BT_PANIC_ATT_MARSHAL_UNMARSHAL_INVALID_STATE
#define PANIC_INVALID_TIMER_ID                              CSR_BT_PANIC_INVALID_TIMER_ID
#define PANIC_DM_ACL_SANITY_FAILED                          CSR_BT_PANIC_DM_ACL_SANITY_FAILED
#define PANIC_DM_CLIENT_ACL_NULL                            CSR_BT_PANIC_DM_CLIENT_ACL_NULL
#define PANIC_DM_AE_INVALID_ADV_HANDLE                      CSR_BT_PANIC_DM_AE_INVALID_ADV_HANDLE
#define PANIC_DM_AE_SET_SCAN_PARAM_FAILED                   CSR_BT_PANIC_DM_AE_SET_SCAN_PARAM_FAILED
#define PANIC_HCISHIM_HCI_SEND_FAILED                       CSR_BT_PANIC_HCISHIM_HCI_SEND_FAILED
#define PANIC_BLUESTACK_UNEXPECTED_HCI_COMMAND_COMPLETE     CSR_BT_PANIC_BLUESTACK_UNEXPECTED_HCI_COMMAND_COMPLETE
#define PANIC_DM_MARSHAL_UNMARSHAL_INVALID_STATE            CSR_BT_PANIC_DM_MARSHAL_UNMARSHAL_INVALID_STATE
#define PANIC_DM_MULTIPLE_ACL_LIST_FOUND                    CSR_BT_PANIC_DM_MULTIPLE_ACL_LIST_FOUND
#define PANIC_L2CAP_READ_CONFTAB_FAILED                     CSR_BT_PANIC_L2CAP_READ_CONFTAB_FAILED
#define PANIC_L2CAP_INVALID_CID                             CSR_BT_PANIC_L2CAP_INVALID_CID
#define PANIC_L2CAP_MBLK_DATA_LEN_MTU_MISMATCH              CSR_BT_PANIC_L2CAP_MBLK_DATA_LEN_MTU_MISMATCH
#define PANIC_L2CAP_MALLOC_FAILED                           CSR_BT_PANIC_L2CAP_MALLOC_FAILED
#define PANIC_L2CAP_CONFIG_BUF_NULL                         CSR_BT_PANIC_L2CAP_CONFIG_BUF_NULL
#define PANIC_L2CAP_FLOW_CTRL_INSTANCE_SANITY_FAILED        CSR_BT_PANIC_L2CAP_FLOW_CTRL_INSTANCE_SANITY_FAILED
#define PANIC_L2CAP_MARSHAL_UNMARSHAL_INVALID_STATE         CSR_BT_PANIC_L2CAP_MARSHAL_UNMARSHAL_INVALID_STATE
#define PANIC_RFCOMM_MARSHAL_UNMARSHAL_INVALID_STATE        CSR_BT_PANIC_RFCOMM_MARSHAL_UNMARSHAL_INVALID_STATE
#define PANIC_SDM_MARSHAL_UNMARSHAL_INVALID_STATE           CSR_BT_PANIC_SDM_MARSHAL_UNMARSHAL_INVALID_STATE
#define PANIC_SDM_CIS_INSTANCE_NOT_FOUND                    CSR_BT_PANIC_SDM_CIS_INSTANCE_NOT_FOUND
#define PANIC_SM_MARSHAL_UNMARSHAL_INVALID_STATE            CSR_BT_PANIC_SM_MARSHAL_UNMARSHAL_INVALID_STATE
#define PANIC_SM_PAIRING_SANITY_FAILURE                     CSR_BT_PANIC_SM_PAIRING_SANITY_FAILURE
#define PANIC_SM_RANDOM_GENERATION_FAILURE                  CSR_BT_PANIC_SM_RANDOM_GENERATION_FAILURE
#define PANIC_SM_INVALID_RPA_TYPE                           CSR_BT_PANIC_SM_INVALID_RPA_TYPE
#define PANIC_SM_ACL_NOT_IN_PAIRING_LIST                    CSR_BT_PANIC_SM_ACL_NOT_IN_PAIRING_LIST
#define PANIC_SM_INVALID_STATE                              BT_PANIC_SM_INVALID_STATE

#endif

#ifdef __cplusplus
}
#endif

#endif

